Digital processors, such as microprocessors, use a computer memory subsystem to store data and processor instructions. Some processors communicate directly with memory, and others use a dedicated controller chip, often part of a “chipset,” to communicate with memory.
Conventional computer memory subsystems are often implemented using memory modules. Referring to FIG. 1, a microprocessor 20 communicates with a memory controller/hub (MCH) 30 that couples the microprocessor 20 to various peripherals. One of these peripherals is system memory, shown as memory modules 40, 42, and 44 inserted in card slots 50, 52, and 54. When connected, the memory modules are addressed from MCH 30 whenever MCH 30 asserts appropriate signals on an Address/Control Bus 60. Data transfers between MCH 30 and one of memory modules 40, 42, and 44 occur on a Data Bus 70. Address/Control Bus 60 and Data Bus 70 are referred to as “multi-drop” buses due to their use of multiple bus stubs for each memory module.
In this prior art system, MCH 30 initiates all memory transactions, all memory write data passes through MCH 30 to the modules, and all memory read data passes through MCH 30 to reach microprocessor 20 or another peripheral (not shown) performing a direct memory access. Absent a functioning MCH or a special purpose prototype MCH, it is impossible to evaluate the performance of address/control bus 60, data bus 70, and the memory modules.